RE: [pci] 66Mhz

["J.D. Bakker" <bakker@thorgal.et.tudelft.nl>]

>Hi!
>
>First I will answer to your question. I synthesised and implemented the
>PCI bridge with CRT core in Virtex II -6 speed grade (xc2v1000-bg575-6)
>without any mayor optimisations and without synthesis constraints. I used
>the ISE 4.2 tool and it managed to meet all timings on input and output
>pins, while PCI clock was 86 MHz and the WISHBONE clock was 97 MHz. Both
>cores together occupied cca 31% of FPGA.

So the PCI+CRT cores take 31% of a 1 million gate FPGA ?? I didn't 
realize the cores were *that* large...

JDB
[who had been planning to do PCI+(modified)CRT in a 200k gates Spartan II]
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