Re: [pci] 66Mhz

["Damjan Lampret" <lampret@opencores.org>]

Heya !

I know that XST generates rather large desegins. I believe that PCI+CRT was
synthesized with Synplify when implemented in XC2S150. So if you say that
Spartan 2 150 is 15% of XCV2 1M gate, then using Synplify with Virtex II 1M
*might* only take 15% (or less since Spartan 2 150 wasn't 100% used). To
verify this somebody will have to run Synplify targetting Virtex 2 and
report his findings. ;-)

regards,
Damjan

----- Original Message -----
From: "J.D. Bakker" <bakker@thorgal.et.tudelft.nl>
To: <pci@opencores.org>
Sent: Friday, September 27, 2002 12:49 PM
Subject: RE: [pci] 66Mhz


> >Hi!
> >
> >First I will answer to your question. I synthesised and implemented the
> >PCI bridge with CRT core in Virtex II -6 speed grade (xc2v1000-bg575-6)
> >without any mayor optimisations and without synthesis constraints. I used
> >the ISE 4.2 tool and it managed to meet all timings on input and output
> >pins, while PCI clock was 86 MHz and the WISHBONE clock was 97 MHz. Both
> >cores together occupied cca 31% of FPGA.
>
> So the PCI+CRT cores take 31% of a 1 million gate FPGA ?? I didn't
> realize the cores were *that* large...
>
> JDB
> [who had been planning to do PCI+(modified)CRT in a 200k gates Spartan II]
> --
> LART. 250 MIPS under one Watt. Free hardware design files.
> http://www.lart.tudelft.nl/
> --
> To unsubscribe from pci mailing list please visit
http://www.opencores.org/mailinglists.shtml
>

--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml