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Re: [openrisc] Verilog version of OpenRISC 1001

To: lampret@opencores.org
Subject: Re: [openrisc] Verilog version of OpenRISC 1001
From: Peter Monta <pmonta@terayon.com>
Date: Mon, 24 Apr 2000 15:14:35 -0700
CC: openrisc@opencores.org
In-reply-to: <006301bfae3a$7c9f63e0$9f07f9c2@gamma> (lampret@opencores.org)
References: <3904A070.2A06A9CD@terayon.com> <006301bfae3a$7c9f63e0$9f07f9c2@gamma>
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org

Hi Damjan,

> what ever you do the code is still beta and I am currently modifying it to
> include current OR1K architecture changes.

Sure, no problem.  I just wanted a feel for the overall structure
and size/speed.  It looked like raw_hazard and carry-flag and a few
other things were in flux.

> 1. What kind of translator did you use (I assume you didn't convert it
> manually)?

Um, manually, actually.  Used a lot of Emacs keyboard macros.

> 2. If translator is freely available we can have automatically translated
> version of OR implementations (OR1003 which is bigger (MMU, caches) is
> underway) also in OpenCores CVS so that you don't have to track changes
> manually.

That would be ideal.  Are there any free translators out there?

Cheers,
Peter Monta   pmonta@terayon.com
Terayon Communication Systems

References:
- [openrisc] Verilog version of OpenRISC 1001
  - From: Peter Monta <pmonta@terayon.com>
- Re: [openrisc] Verilog version of OpenRISC 1001
  - From: "Damjan Lampret" <lampret@opencores.org>

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