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Re: [openrisc] Verilog version of OpenRISC 1001

To: <openrisc@opencores.org>, <pmonta@terayon.com>
Subject: Re: [openrisc] Verilog version of OpenRISC 1001
From: "Damjan Lampret" <lampret@opencores.org>
Date: Tue, 25 Apr 2000 00:14:39 +0200
Cc: <geda-dev@geda.seul.org>
Organization: OPENCORES.ORG
References: <3904A070.2A06A9CD@terayon.com>
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org

Hi Peter,

what ever you do the code is still beta and I am currently modifying it to
include current OR1K architecture changes.

I have two questions:

1. What kind of translator did you use (I assume you didn't convert it
manually)?
2. If translator is freely available we can have automatically translated
version of OR implementations (OR1003 which is bigger (MMU, caches) is
underway) also in OpenCores CVS so that you don't have to track changes
manually.

regards, Damjan

----- Original Message -----
From: Peter Monta <pmonta@terayon.com>
To: <openrisc@opencores.org>
Cc: <geda-dev@geda.seul.org>
Sent: Monday, April 24, 2000 9:28 PM
Subject: [openrisc] Verilog version of OpenRISC 1001

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- [openrisc] Verilog version of OpenRISC 1001
  - From: Peter Monta <pmonta@terayon.com>

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