Re: [openrisc] Re: Hi BOTH,

[Usef Saiful-Ulum <usef@vlsi.itb.ac.id>]

Hi all,

On Mon, 10 Apr 2000, Damjan Lampret wrote:

> > Hi Damjan,
> > if possible, could the core be OR1600?(since I think the ISA is OR16)

What do you mean the ISA is OR16? Doesn't it mix the OR32 and OR16?

> Of course it can be. But should I rename my 1001 and 1003 to something else?
> What numbers in OR1000 mean?

Do you plan to release some versions of OR1K or what? Please inform me, I
didn't notice the recent status of OR1K.

> I think something like this:
> 
> 1000 is general architecture. So an actual implementation must have the
> first number 1xxx if it is compliant to OR1000 architecture. Perhaps second
> number should identify to which subclass it belogs or which ISA implements?
> Any third and fourth numbers should be version numbers. Something like that
> ...
> 
> Suggestions? Ideas?

This would be very flexible, since you have 1000 combinations for the last
3 numbers, you should partition it to major/minor number. Major number
should tell whether it is 32 bit/64 bit etc, whether it implements FPU or
other functional unit or not, etc. Minor number should refer to the
current status, even = stable, etc. The first two should be major number
and the rest = minor number.

The last is my question, very basic:
Why don't you implement conditional execution of instruction (like ARM,
TMS320 family, etc) since that would reduces costly branching and
increases parallelism for higher sustained performance?


Kind regards,

Usef