Re: [oc] synthesizable divider

[Mathias Johansson <e96mjh@home.se>]

At 18:33 2002-06-07 +0000, you wrote:
>On Friday 07 June 2002 08:30, milacn wrote:
> > hello, Currently I am working on a project that needs division algorithm,
> > but i have no idea about it, how can i implement a synthesizable divider
> > using vhdl or verilog? should i use combinational or sequential circuit?
> >
> > thanks a lot!
>
>
>Try a sequential circuit first, consisting of about 2 dozen nand
>gates and about three RC elements. Hock them up to form a
>analog PLL. Use that to lock to your original clock and generate
>a lower clock as desired.
>
>And tomorrow we will feature "How to make a transistor from
>household chemicals, by Sigmund Freud"
>rudi

Helo,

Wow, I will be very much intrested in this projekt, for I need such thing 
in my final exam! Deadline is due in three days and I have no idea where to 
start!! Send me mr Freud's work right now!!! (please.) Am waitink for your 
response!

Lol. I'm sorry, couldn't resist it.
/Mathias

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