Re: [oc] synthesizable divider

[Rudolf Usselmann <rudi@asics.ws>]

On Friday 07 June 2002 08:30, milacn wrote:
> hello, Currently I am working on a project that needs division algorithm,
> but i have no idea about it, how can i implement a synthesizable divider
> using vhdl or verilog? should i use combinational or sequential circuit?
>
> thanks a lot!


Try a sequential circuit first, consisting of about 2 dozen nand
gates and about three RC elements. Hock them up to form a
analog PLL. Use that to lock to your original clock and generate
a lower clock as desired.

And tomorrow we will feature "How to make a transistor from
household chemicals, by Sigmund Freud"

rudi


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