Re: [oc] synthesizable divider

[Sridhar Nandula <sridhar.nandula@dcmtech.co.in>]

Can u elaborate your question? Like bit width, frequency limit, etc....
One option is to use direct LPM component from Altera Megafunction or some 
other tools... i did some work on divider. I may be able to help you.

Regards,
Sridhar Nandula
Design Engineer,
125, Phase1,
Udyog vihar, Gurgaon
Ph: (+91) 0124-6439224 ext 232
Email: nandulasridhar@yahoo.com


On Friday 07 June 2002 02:00 pm, you wrote:
> hello, Currently I am working on a project that needs division algorithm,
> but i have no idea about it, how can i implement a synthesizable divider
> using vhdl or verilog? should i use combinational or sequential circuit?
>
> thanks a lot!
>
>
>
> ______________________________________
>
> ===================================================================
> 新浪免费电子邮箱 (http://mail.sina.com.cn)
> 新浪分类信息：二手市场走一走，该出手时就出手！
> (http://classad.sina.com.cn/2shou/)
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml