[pci] BUS Mastering & TRDY generation ?

[Gustaw47@poczta.onet.pl]

Hi all,

I try to implement BUS Mastering on my PCI Card.
The card asserts REQ , Mainboard asserts GNT. Then I invoke addres 
phase : Memory Read + some addres (tried different adresses), IRDY. 
Mainboard still holds GNT (bus is mine) but never asserts TRDY so no 
data can be transferred.
Finally I must deassert REQ and transaction fails to complete.

What could be a reason that Mainboard doesn't assert TRDY ? I work in 
the simplest enviroment : DOS, Real mode, software in ASM.

The second question is:
If I use BAR Registers and reserve some MEMORY space for my card, 
where phisically will it be located ? On mainboard's SD-RAM or in my 
card's S-RAM ?

Maybe I post trivial questions, but I didn't find any information about it 
anywhere, even in PCI SIG Specifications ...

Thanks in advance,
Gustaw Mazurek, Warsaw.
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