Re: [openrisc] OR1200 problem

[Shawn Tan <shawn.tan@aeste.net>]

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Damjan Lampret wrote:
| Very obvious answers would be:
| 1. If you don't apply reset.
Well, I did apply reset.. for 10 clock cycles..

| 2. If it fetches instructions, that are not really instructions
They're simple jump instructions.. 0x00000001.. They work on the
synthesized netlist.. not the RTL code..

I think that it might be a simulator problem.. because I've got another
issue with another core.. for the memory controller core, the RTL works
fine, but the synthesized netlist doesn't.. (:

I don't think that it's a real problem.. I'll take whatever works for now..

thanks..

With Metta,
Shawn Tan.
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iD8DBQE8xgrk9KUEj/m6O5oRAoXfAJsFXKXneVIxnNj2ndcMfz/6sTUb8wCgjwQd
NIhYnOnCjmxgTwT4Sz62kqk=
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