|
Hello
I'm working on an electronic project, in which I do
save and re-read data into SDRAM (same as FIFO)
Write speed is 100MHz, 12M x 16bits (3 chips of
4M16)
Read can be slowly
Not any data must be lost
I want to use Altera Nios developpement kit and
Cyclone or Flex FPGA
Do you have a source for a sdram controller IP, and
could you send me ?
How can I do it ?
Thanks
Dominique BRANCHE
|