[openip] Need an "exceptional" public VHDL project

[Mark Hampton <mark.hampton@certess.com>]

Hi,

Would anyone be able to recommend a VHDL RTL opencores project (ideally not 
too large e.g. a peripheral) which meets the following criteria :

1) Has a testbench providing "good" coverage
2) The testbench is automated i.e provides a "go/no go" indication
3) The testbench has a regression suite
4) The project was kept under version control during development
5) The project was regularly checked in during development (both RTL + 
testbench)

Thanks for any help.

   Mark

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