Re: [nnARM] I think that...

["shen shengyu" <shengyu_shen@hotmail.com>]

Hi Fancy

You have discover an error

in WishBone protocol, the rst_i==1'b1 means reset, I have make a mistake in 
"negedge rst_i", it must be "posedge rst_i"

thank you very much

Best Regard

BTW : if we have been contact before this time?

please keep contact and do not hesitate to mail me if you have any problem.

ShengYu Shen
National University of Defence Technology of China
Cell phone +86 130 17382201
mail : syshen@nudt.edu.cn
shengyu_shen@hotmail.com
shengyu_shen@opencores.org



>From: fancy77@263.net
>Reply-To: nnarm@opencores.org
>To: nnarm@opencores.org
>Subject: [nnARM] I think that...
>Date: Fri, 12 Oct 2001 08:52:25 +0200
>
>I think that the behavioral module of MemoryController
>(MemoryController_WB_Beh.v) should be put put into testbench.
>
>
>I think there is a bug in the I_Bus2Core.v :
>-----------------------------------------------------------
>-      always	@(posedge clk_i or negedge rst_i)
>-     begin
>-	if(rst_i==1'b1)
>-	begin
>-		//this value can not be same as init PC
>-		CurrentAddress=32'hffffffff;
>-		CurrentInstruction=`InstructionZero;
>-	end
>-           ...
>------------------------------------------------------------
>    the if statement should be :  if(rst_i==1'b0)
>    because the trigger event is on the negedge of rst_i
>--
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