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[nnARM] I think that...
I think that the behavioral module of MemoryController
(MemoryController_WB_Beh.v) should be put put into testbench.
I think there is a bug in the I_Bus2Core.v :
-----------------------------------------------------------
- always @(posedge clk_i or negedge rst_i)
- begin
- if(rst_i==1'b1)
- begin
- //this value can not be same as init PC
- CurrentAddress=32'hffffffff;
- CurrentInstruction=`InstructionZero;
- end
- ...
------------------------------------------------------------
the if statement should be : if(rst_i==1'b0)
because the trigger event is on the negedge of rst_i
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