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[cvs-checkins] ethernet/rtl/verilog eth_transmitcontrol.v eth ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_transmitcontrol.v eth ...
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Tue, 19 Nov 2002 16:37:33 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/11/19 16:37:33

Modified files:
	rtl/verilog    : eth_transmitcontrol.v eth_maccontrol.v 

Log message:
	When control frame (PAUSE) was sent, status was written in the
	eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
	Only TXC interrupt is set.

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