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[cvs-checkins] ethernet/rtl/verilog eth_rxethmac.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_rxethmac.v
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Tue, 19 Nov 2002 16:35:36 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/11/19 16:35:36

Modified files:
	rtl/verilog    : eth_rxethmac.v 

Log message:
	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
	that a frame was received because of the promiscous mode.

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