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[cvs-checkins] ethernet/rtl/verilog eth_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_top.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Wed, 4 Sep 2002 17:44:12 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/09/04 17:44:12

Modified files:
	rtl/verilog    : eth_top.v 

Log message:
	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
	connected.
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