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[cvs-checkins] pci/ tl/verilog/pci_target32_sm.v ench/verilog ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] pci/ tl/verilog/pci_target32_sm.v ench/verilog ...
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Thu, 22 Aug 2002 08:07:14 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/08/22 08:07:14

Modified files:
	rtl/verilog    : pci_target32_sm.v 
	bench/verilog  : system.v 
	sim/rtl_sim/run: top_groups.do 

Log message:
	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
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