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[cvs-checkins] pci/rtl/verilog pci_ram_16x40d.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] pci/rtl/verilog pci_ram_16x40d.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Mon, 19 Aug 2002 15:49:39 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/08/19 15:49:39

Added files:
	rtl/verilog    : pci_ram_16x40d.v 

Log message:
	Extracted distributed RAM module from wb/pci_tpram.v to its own file
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