[cvs-checkins] irda/ ench/verilog/irda_test.v tl/verilog/irda ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	irda
Changes by:	gorban	02/07/29 20:50:54

Modified files:
	bench/verilog  : irda_test.v 
	rtl/verilog    : irda_defines.v 
	sim/rtl_sim/run: run_sim 
Added files:
	bench/verilog  : irda_sir_test.v 
	doc            : README 
	rtl/verilog    : irda_top_sir_only.v uart_debug_if.v 
	                 uart_for_irda_defines.v uart_receiver.v 
	                 uart_regs.v uart_rfifo.v uart_tfifo.v 
	                 uart_top.v uart_transmitter.v uart_wb.v 
	sim/rtl_sim/bin: nc_sir.scr 
	sim/rtl_sim/run: run_sir_sim 

Log message:
	Added the reduced version of IrDA core.
	It is SIR mode only (up to 115.2Kbit) based on UART.
	The uart16550 with modified defines is included with the IrDA sources.
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