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[cvs-checkins] mem_if/rtl/verilog mem_if_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] mem_if/rtl/verilog mem_if_top.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Thu, 25 Jul 2002 13:17:56 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	mem_if
Changes by:	mihad	02/07/25 13:17:56

Modified files:
	rtl/verilog    : mem_if_top.v 

Log message:
	Another cycle signal for register access added.
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