[cvs-checkins] uart16550/rtl/verilog uart_debug_if.v uart_def ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	02/07/22 22:02:25

Modified files:
	rtl/verilog    : uart_debug_if.v uart_defines.v uart_receiver.v 
	                 uart_regs.v uart_top.v uart_transmitter.v 
	                 uart_wb.v 
Added files:
	rtl/verilog    : raminfr.v uart_rfifo.v uart_tfifo.v 

Log message:
	Bug Fixes:
	* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
	Problem reported by Kenny.Tung.
	* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
	
	Improvements:
	* Made FIFO's as general inferrable memory where possible.
	So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
	This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
	
	* Added optional baudrate output (baud_o).
	This is identical to BAUDOUT* signal on 16550 chip.
	It outputs 16xbit_clock_rate - the divided clock.
	It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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