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[cvs-checkins] or1k/mp3/rtl/verilog/or1200 or1200_dpram_32x32 ...

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	02/01/23 08:52:56

Modified files:
	mp3/rtl/verilog/or1200: or1200_dpram_32x32.v or1200_except.v 
	                        or1200_sprs.v 

Log message:
	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.

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