CVSROOT: /home/oc/cvs Module name: or1k Changes by: ivang 02/01/08 16:22:38 Modified files: or1ksim/testbench: mc_async.c mc_sync.c mc_dram.c mc_ssram.c mc_common.h Log message: Added GPIO output for progress indication for FPGA simulation. -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml