[cvs-checkins] uart16550/rtl/verilog uart_transmitter.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	02/01/08 12:29:45

Modified files:
	rtl/verilog    : uart_transmitter.v 

Log message:
	tf_pop was too wide. Now it is only 1 clk cycle width.

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