[cvs-checkins] uart16550/rtl/verilog uart_receiver.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/11/27 23:17:15

Modified files:
	rtl/verilog    : uart_receiver.v 

Log message:
	Fixed bug that prevented synthesis in uart_receiver.v

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