[cvs-checkins] or1k/mp3/rtl/verilog/or1200 defines.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	01/11/27 20:46:57

Modified files:
	mp3/rtl/verilog/or1200: defines.v 

Log message:
	Now FPGA and ASIC target are separate.

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