[cvs-checkins] uart16550/rtl/verilog uart_defines.v uart_fifo ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/11/26 22:38:58

Modified files:
	rtl/verilog    : uart_defines.v uart_fifo.v uart_receiver.v 
	                 uart_regs.v 

Log message:
	Lots of fixes:
	Break condition wasn't handled correctly at all.
	LSR bits could lose their values.
	LSR value after reset was wrong.
	Timing of THRE interrupt signal corrected.
	LSR bit 0 timing corrected.

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