[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] dbg_interface/rtl/verilog dbg_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] dbg_interface/rtl/verilog dbg_top.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Wed, 14 Nov 2001 11:10:45 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	dbg_interface
Changes by:	mohor	01/11/14 11:10:45

Modified files:
	rtl/verilog    : dbg_top.v 

Log message:
	Wishbone data latched on wb_clk_i instead of risc_clk.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml

Prev by Date: [cvs-checkins] or1k/or1ksim/testbench/uos tick.c uos.c
Next by Date: [cvs-checkins] ethernet/sim/rtl_sim/run top_modelsim.do
Prev by thread: [cvs-checkins] dbg_interface/rtl/verilog dbg_top.v
Next by thread: [cvs-checkins] dbg_interface/rtl/verilog dbg_top.v
Index(es):
- Date
- Thread