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[cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_wishbon ...



CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	01/11/13 15:24:02

Modified files:
	rtl/verilog    : eth_defines.v eth_wishbonedma.v 

Log message:
	Generic memory model is used. Defines are changed for the same reason.

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