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[cvs-checkins] uart16550/rtl/verilog uart_fifo.v uart_receive ...

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/11/07 18:51:57

Modified files:
	rtl/verilog    : uart_fifo.v uart_receiver.v uart_regs.v 
	                 uart_top.v uart_transmitter.v 

Log message:
	Heavily rewritten interrupt and LSR subsystems.
	Many bugs hopefully squashed.

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