[cvs-checkins] dbg_interface/bench/verilog dbg_tb.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	dbg_interface
Changes by:	mohor	01/10/19 13:39:21

Modified files:
	bench/verilog  : dbg_tb.v 

Log message:
	dbg_timescale.v changed to timescale.v This is done for the simulation of
	few different cores in a single project.

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