CVSROOT: /home/oc/cvs Module name: dbg_interface Changes by: mohor 01/10/19 13:39:03 Modified files: sim/rtl_sim/run: do.do Log message: dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project. -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml