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[cvs-checkins] wb_dma/rtl/verilog wb_dma_ch_pri_enc.v wb_dma_ ...
CVSROOT: /home/oc/cvs
Module name: wb_dma
Changes by: oc 01/10/19 06:35:08
Modified files:
rtl/verilog : wb_dma_ch_pri_enc.v wb_dma_ch_rf.v
wb_dma_ch_sel.v wb_dma_defines.v
wb_dma_pri_enc_sub.v wb_dma_rf.v wb_dma_top.v
wb_dma_wb_if.v wb_dma_wb_slv.v
Log message:
- Made the core parameterized
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