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[cvs-checkins] rtc/ ench/verilog/tb_defines.v ench/verilog/tb ...

CVSROOT:	/home/oc/cvs
Module name:	rtc
Changes by:	lampret	01/09/19 00:55:39

Modified files:
	bench/verilog  : tb_defines.v tb_tasks.v tb_top.v 
	sim/rtl_sim/bin: sim.sh 
Added files:
	rtl/verilog    : rtc_defines.v rtc_top.v 

Log message:
	Changed rtc into rtc_top. Changed defines.v into rtc_defines.v. Fixed a bug with two defines for alarms.

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