[cvs-checkins] uart16550/rtl/verilog timescale.v uart_defines ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/08/24 23:01:12

Modified files:
	rtl/verilog    : timescale.v uart_defines.v uart_fifo.v 
	                 uart_receiver.v uart_regs.v uart_top.v 
	                 uart_transmitter.v uart_wb.v 

Log message:
	Things connected to parity changed.
	Clock devider changed.

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