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[cvs-checkins] uart16550/rtl/verilog uart_defines.v
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: mohor 01/08/23 17:22:51
Modified files:
rtl/verilog : uart_defines.v
Log message:
Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.
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