[cvs-checkins] Import

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	irda
Changes by:	oc	01/08/21 22:06:49

Log message:
    Status:
    
    Vendor Tag:	gorban
    Release Tags:	First
    
    N irda/.keepme
    N irda/bench/.keepme
    N irda/bench/verilog/crc_ccitt16_test.v
    N irda/bench/verilog/crc_test.v
    N irda/bench/verilog/.keepme
    N irda/bench/verilog/irda_test.v
    N irda/bench/vhdl/.keepme
    N irda/doc/IrDA_spec.pdf
    N irda/doc/.keepme
    N irda/doc/src/.keepme
    N irda/fv/.keepme
    N irda/lint/.keepme
    N irda/lint/bin/.keepme
    N irda/lint/log/.keepme
    N irda/lint/out/.keepme
    N irda/lint/run/.keepme
    N irda/rtl/.keepme
    N irda/rtl/verilog/irda_fir_bit_sync.v
    N irda/rtl/verilog/irda_fir_flag_det.v
    N irda/rtl/verilog/irda_mir_tx.v
    N irda/rtl/verilog/irda_mir_break_det.v
    N irda/rtl/verilog/irda_data_ctrl.v
    N irda/rtl/verilog/irda_fir_flag_gen.v
    N irda/rtl/verilog/irda_mir_rx.v
    N irda/rtl/verilog/irda_interrupts.v
    N irda/rtl/verilog/irda_sir_decoder.v
    N irda/rtl/verilog/irda_sip_gen.v
    N irda/rtl/verilog/irda_out_mux.v
    N irda/rtl/verilog/irda_reg.v
    N irda/rtl/verilog/irda_mir_data_ctrl.v
    N irda/rtl/verilog/irda_mir_decoder.v
    N irda/rtl/verilog/irda_mir_encoder.v
    N irda/rtl/verilog/irda_fir_tx.v
    N irda/rtl/verilog/irda_mir_st_gen.v
    N irda/rtl/verilog/.keepme
    N irda/rtl/verilog/irda_sir_encoder.v
    N irda/rtl/verilog/irda_fir_4ppm_decoder.v
    N irda/rtl/verilog/irda_top.v
    N irda/rtl/verilog/irda_fast_enable_gen.v
    N irda/rtl/verilog/irda_defines.v
    N irda/rtl/verilog/irda_fir_rx.v
    N irda/rtl/verilog/irda_mir_st_det.v
    N irda/rtl/verilog/irda_master_register.v
    N irda/rtl/verilog/irda_mir_bit_stuffer.v
    N irda/rtl/verilog/irda_crc32_rx.v
    N irda/rtl/verilog/irda_wb_router.v
    N irda/rtl/verilog/irda_wb.v
    N irda/rtl/verilog/irda_fifo.v
    N irda/rtl/verilog/irda_crc32.v
    N irda/rtl/verilog/irda_fir_4ppm_encoder.v
    N irda/rtl/verilog/irda_mir_bit_destuffer.v
    N irda/rtl/verilog/irda_crc_ccitt16.v
    N irda/rtl/verilog/irda_crc_rx_ccitt16.v
    N irda/rtl/verilog/timescale.v
    N irda/rtl/vhdl/.keepme
    N irda/sim/.keepme
    N irda/sim/gate_sim/.keepme
    N irda/sim/gate_sim/bin/.keepme
    N irda/sim/gate_sim/log/.keepme
    N irda/sim/gate_sim/out/.keepme
    N irda/sim/gate_sim/run/.keepme
    N irda/sim/gate_sim/src/.keepme
    N irda/sim/rtl_sim/.keepme
    N irda/sim/rtl_sim/bin/nc.scr
    N irda/sim/rtl_sim/bin/sim.tcl
    N irda/sim/rtl_sim/bin/.keepme
    N irda/sim/rtl_sim/log/.keepme
    N irda/sim/rtl_sim/out/.keepme
    N irda/sim/rtl_sim/run/run_sim
    N irda/sim/rtl_sim/run/run_signalscan
    N irda/sim/rtl_sim/run/.keepme
    N irda/sim/rtl_sim/src/.keepme
    N irda/syn/.keepme
    N irda/syn/bin/.keepme
    N irda/syn/log/.keepme
    N irda/syn/out/.keepme
    N irda/syn/run/.keepme
    N irda/syn/src/.keepme
    
    No conflicts created by this import
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