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[cvs-checkins] rtc/ ench/verilog/clkrst.v ench/verilog/tb_def ...
CVSROOT: /home/oc/cvs
Module name: rtc
Changes by: lampret 01/08/21 14:53:11
Added files:
bench/verilog : clkrst.v tb_defines.v tb_tasks.v tb_top.v
timescale.v wb_master.v
rtl/doc : rtc_spec.pdf
rtl/verilog : defines.v rtc.v
Log message:
Changed directory structure, uniquified defines and changed design's port names.
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