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Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
Aloha!
Niclas Hedhman wrote:
> I heard Sweden now has reached an ultimate tax form.
> Only has a single field; Sign here!
> (implying you take full responsibility for the tax departments calculation and
> collection of taxable income).
>
> Joachim, isn't it so.
Yes.
Dunno if that is best expressed in SystemC, Verilog or VHDL though...
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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