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Re: [oc] any sugestions??
What the problem with simili ?
Does Visibly work well ?
nicO
On Mon, 14 Oct 2002 22:09:02 +0100
Shehryar Shaheen <shehryar.shaheen@ul.ie> wrote:
> U could use ModelSim with starter license for Simulation
> There will be no limit on the size of the code but the simulation speed
> for code sizes larger than the starter license limit will be very slow. If
> your
> machine is fast this can be compensated to some extent. It has graphical
> waveform,data path and other displays.
>
> Or u could use VHDL Simili with a free Tcl/Tk script Visibly which can
> display the .lst file generated by VHDL Simili in the form of a wave
> but in my opinion modelsim starter is still a better choice
>
> For synthesis u can use WebPackISE from Xilinx it's free
> It can hadle designs upto 300,000 gates which is a fair
> deal for free!
> The new WebPack also has support for
> Virtex II Pro (the smallest Virtex II Pro which does not
> have PowerPC embedded in the FPGA fabric :( but again
> it's a fair deal for free!)
>
>
> Hope this Helps
>
> Shehryar
>
> ----- Original Message -----
> From: "Friman Sanchez Castaño" <fsanchez@ac.upc.es>
> To: <cores@opencores.org>
> Sent: Monday, October 14, 2002 6:44 PM
> Subject: [oc] any sugestions??
>
>
> > Hi...
> >
> > I am looking for a FREE :
> > *tool to simulate vhdl code.. without restrictions? with graphic
> interface.
> > *tool to sinthetize vhdl code?
> >
> >
> > thanks in advances..!!
> >
> >
> > Friman S.C
> >
> >
> >
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