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[oc] Code Coverage
Hi All,
I have started using the “nccov” tool for code coverage of verilog code.
It is the tool that comes along with NC Verilog. I am getting the reports
in terms of percentage of statements, expressions and FSMs. But how
to get exactly the reports about the part of the RTL not covered in the
test bench?
Can anybody suggest some more tools for code coverage?
Thanks in advance,
Regards,
Vlsi Champ....
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