Re: [oc] Volunteer for GPL'd CAD tool

["Tantos Andras" <andras_tantos@yahoo.com>]

Hi!

> > > Proprietary CAD tools have the usual inconvenience of proprietary
> > > software. They are impossible to debug for the end user, the
> > > interfaces and file formats are not unified, each manufacturer
> > > redesigns its own place and route algorithms... It is obviously a
> > > stupid waste of time and intellectual effort.
> >
> > That's probably true. However all C/C++ compiler team implements the
same
> > optimization algorithms. That's also a 'stupid waste of time and
> > intellectual effort'. Even when GCC is there for more than a decade... I
> > don't think you could change that.
> This is not a waste of intellectual effort. Intel has its own compiler
> for its cpus, yet I don't know anyone using it.
> Just like cpu-compiler, FPGA-PAR SW is undividable.
> So even if Xilinx would not be successful selling their PAR SW,
> they would have to develop it to continue developing their chips.

OK, I wasn't clear enough. I thought something like that too, and wanted to
point out that no in-house development is a mare 'waste of time and
intellectual effort'. I ment to say that there *should* be some reason for
companies continue developing their own proprietary compilers even when GCC
is there. One of the reasons is what you've mentioned. Another is that they
think they can make a better compiler than GCC, another is that they don't
want to depend on any third-party SW (like MS I suppose).

>
> > Hmmm... I would say, the idea is great. But! I would give everyone the
> > opportunity to implement their own back-end without joining the open
> effort.
> > I mean: Xilinx would probably still maintain it's own PAR (back-end in
> your
> > words) but if it would be compatible with your front-end the world would
> be
> > much nicer already. So I'dd suggest creating an open and detailed
> > specification of the interface between the front-end and the back-end,
and
> > leave the choice open to use any front-end with any back-end. And once
> > again: isn't EDIF something like that already?
> Xilinx has a lot of patents on FPGAs. Maybe some of them cover also SW?

There are many third party tools out there that can interface to the Xilinx
tool-chain. FPGA Express, Leonardo Spectrum, etc. As far as I know they
create an EDIF netlist form the VHDL/Verilog source and feed it to the
Xilinx tools. Same goes for Altera (their integrated VHDL was so bad you
didn't really even have a choice). I wouldn't think it would be a patent
infringement to implement another (GPL) tool, doing the same.

Andras Tantos


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