[oc] A Query Regarding Xilinx PAR

[harshit.suri@st.com]

     Hello Everyone..I am working on EDA development and am interested to 
     know WHEN DOES a designer(user of the Xilinx FPGA EDA tool) ,use the 
     "ignore timing constraints" option in the xilinx design flow.I want to 
     know why and when would he use this option in the design tool,inspite 
     of him specifying timing constraints..I would be happy if i could get 
     a broad spectrum of answers from all the designers out there so that i 
     could understand this issue better..
     
     Best Regards 
     Harshit Suri

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