[oc] Problem with Risc5x core

["MikeJ" <mikej@opencores.org>]

> Hi !
>
> Might be a problem with the prescaler - although the core is pretty well
> tested now, the timer has really not been fully exercised yet. I'll have a
> look at it this weekend and extend the test suite to cover it.
>
> I've had a few requests for hexfile translators. I have a little C program
> that takes in a .hex file and drops out ucf / attribute init statements
for
> synthesis. Again, I'll release it over the weekend once I've tidied it up
a
> bit.
>
> I have two cores in the same chip running here with some tiny Xilinx
> specific uarts attached - and am using one to serial download programs &
> monitor the other. Hope to get to full status readback, single step etc.
>
> Cheers,
> Mike.
>
>
> > hi Mike,
> >
> > I 've downloaded your micro core. Really nice core !!
> > I've implemented it in an Xilinx Virtex E. I don't use the 'VIRTEX'
> > architectures, instead I use the 'RTL' architecture.
> > I wrote a few test programs and found the following problem:
> >
> > Part from test program
> >
> > Timer0 equ H'001e'
> >
> > start movlw 0xaa
> > loop decfsz Timer0,f
> >        goto loop
> >
> >        rest from program
> >
> > The File timer0 is allways decrememted by 2 and not by 1 !!
> > If I preset the file to 0xff ist counts 0xff, 0xfd, 0xfb. Therefore it
> comes
> > to 0x03, 0x01 and then to 0xff. The Z-Flag is never set.
> > Can you explain it ???
> >
> >
> > And a second question:
> > How can you (I) translate a hex-file in the form that the DPRAM -Init
> > Attritbutes are set correctly ?
> >
> >
> > Best regards
> > and go on with this nice design
> >
> <snip>
>

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