Re: [oc] Re: How to create such signal wave using VHDL?

["David I. Lehn" <dlehn@vt.edu>]

* Paul McFeeters <paul.mcfeeters@ntlworld.com> [20011221 16:52]:
> 
> Verilog to C translator? Na it will never catch on! lol
> Too much eggnog?
> 

(yeah that was just refering to a typo but...)

Language translation is a perfectly good way to implement a simulator.
Hard code event loops and logic where possible and let a C compiler
optimize it for you.

-dave
-- 
David I. Lehn <dlehn@vt.edu>  | http://www.lehn.org/~dlehn/
Computer Engineering Graduate @ Virginia Tech in sunny Blacksburg, VA
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