RE: [oc] Re: How to create such signal wave using VHDL?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Verilog to C translator? Na it will never catch on! lol
Too much eggnog?

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Marko Mlinar
> Sent: 21 December 2001 12:06
> To: cores@opencores.org
> Subject: Re: [oc] Re: How to create such signal wave using VHDL?
> 
> 
> > Marko,
> >
> > find a opencore for Ethernet, implement it and then use the TCPsocket
> implementation
> > off a copy of Linux and translate the C into Verilog (or VHDL if you are
> brave).
> > Not bad for 10seconds of thinking egh? Anything I missed?
> 
> Don't want to argue - but of course:
> - first you have to use Igor's Ethernet, which shouldn't be a problem
> - you have to make wishbone interface in VERILOG
> - supposingly your C to Verilog tool works (if you have 10k$ to buy it) you
> still
> have to:
> - obtain TCP/IP stack from e.g. Linux
> - change the behaviour of TCP/IP from SW behaviour to more like HW one,
> which is IMHO
>   not an easy task and change programming interface. I suppose you don't
> have malloc
>   or files supported with translator.
> - obtain (= buy) sythesis software
> - meet timing constraints, maybe not so simple
> - buy a couple of big FPGAs to fit the whole design, because the Verilog to
> C translator yields
>   big code...
> 
> IMHO this is at least 2my of hard work...
> 
> Marko
> 
> 
> --
> To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml