Re: [oc] synthesis problem with uart16550

[Pavel Korensky <pavelk@anet.cz>]

At 04:11 PM 9/28/01 +0200, you wrote:
>Hi,
>
>during the synthesis of the uart16550 verilog code with xilinx xst
>synthesis tool(included in the webpak software suite)
>I got this warning that later results in an error:
>
>WARNING : (FCT__0306). Multi-source on signal <shift_out<0>> not
>replaced by logic
>
>I get this warning for every bit of the shift_out register.
>
>I think it is not an error in the design. The diffenret assignments are
>made by different cases in a state maschine.
>So what could be my problem ? Any idea ?

Set the Wired_OR logic in synthesis tool.

Best regards

PavelK


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