[oc] synthesis problem with uart16550

[Matthias Fuchs <matthias.fuchs@esd-electronics.com>]

Hi,

during the synthesis of the uart16550 verilog code with xilinx xst
synthesis tool(included in the webpak software suite)
I got this warning that later results in an error:

WARNING : (FCT__0306). Multi-source on signal <shift_out<0>> not
replaced by logic

I get this warning for every bit of the shift_out register.

I think it is not an error in the design. The diffenret assignments are
made by different cases in a state maschine.
So what could be my problem ? Any idea ?

Matthias
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