No Subject

[sandeep shastri <sandeep_shastri@yahoo.com>]

Dear Sir,
As I am working on Image compression using VHDL
on Xilinx tool and supposing you might have an
idea about Xilinx, I have some doubts, which if
you can solve will make it  possible for me to go
ahead.
1)I am getting much warnings while
synthesis.Whether it affects the design.
2)Is there any criteria about programing in VHDL
by taking into consideration the archiecture of
FPGA.
3)Can we get the signals defined  in the program
to be viewed while simulation.
4) How to overcome the simulation difficulties
while timing simulation.
       If you help me in this regard i will be
obliged.
             thanks

                   


=====
Sandeep S. Shastri
10, Ravishree,
S.B.H.Colony,
Ambajogai Road,
Latur-413531
Phone No. :-02382-27230(R)
            02382-22230(O)

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